module data_memory(
input [7:0] add, //address of data
input [7:0] wd, //write data
input clk, wb, rb, //clock, write bit, read bit
output [7:0] rd //read data
); //data memory

reg [7:0] data [255:0]; //256 registers(8-bit)

assign rd = data[add>>2];

always @ (negedge clk) begin

if(wb) 
data[add>>2]=wd;
end

endmodule